BETA firmware PLL fix

General discussion and support for the Peaberry SDR V2.

BETA firmware PLL fix

Postby AE9RB » Sun Mar 01, 2015 11:14 pm

While working on Peaberry CW I noticed a rare occasion where the analog PLL in the PSoC didn't get an ideal lock. If you have ever found that you needed to start up your Peaberry a second time to clear an audio glitch, this fix will make sure it always works on the first boot. I know of only one report of this condition so I assume it's pretty rare.

This fix will also provide some diagnostics for the analog and digital PLLs in the PSoC. If the LED flashes erratically only when the USB cable is plugged in, the PLLs are failing to lock. It is also now normal for the LED to flash a few times on startup when the USB cable is plugged in. Each flash is the firmware nudging the PLL into an ideal lock and more or less flashes doesn't mean anything. Only if it doesn't stop flashing do you have a problem.

It's possible that I was too aggressive detecting this condition and some radios will never lock. So I won't ship this in kits until it is well tested on a variety of hardware. Please help by loading this on your Peaberry V2 (how to is in Appendix of manual). Let me know if your radio doesn't lock with this firmware. You can restore the old firmware if you have problems so don't worry about making your radio unusable.
Attachments
BETA2015MAR01peaberryV2.zip
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73 David AE9RB
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Re: BETA firmware PLL fix

Postby edmurphy » Thu Mar 05, 2015 9:51 am

Hello David,
I loaded your PLL code. I am finding that I still have a very unstable 12.288MHz signal being displayed on HDSDR. This signal I take is the Codec clock ? Is it normal to have a very broadband signal at that frequency ? I also notice that there are several very unstable oscillations at frequencies either side of the PSoC 36.923MHz clock. These frequencies are approximately 36.807, 36.867, 36.984, 37.044, 37.103, 37.162 and there are others .This condition is present when the USB lead is connected to the PC. If I then disconnect the USB I then get several stable carriers either side of the 36.923MHz clock. The LED was indicating that there was a good lock at the time.

The condition described above is the same with the original firmware.

Hope this is of interest.

Regards Ed
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Re: BETA firmware PLL fix

Postby AE9RB » Thu Mar 05, 2015 8:05 pm

Thanks for testing the new firmware, Ed.

That's the main clock coming from a fractional-N PLL. It's phase locked to the USB clock from your computer. Average frequency is 36.864 (more or less depending on the accuracy of the USB host). Tuning to 12.288MHz will pick this up as a 3rd harmonic. It's not clear what you're after. Are you trying to use the Peaberry outside the ham bands? It's definitely not designed for that.
73 David AE9RB
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Re: BETA firmware PLL fix

Postby pilotcfii » Mon Mar 09, 2015 1:45 pm

David,
I just installed the Beta firmware and it seems to work OK thus far. I get one flash of the LED after power on, so I guess the clock is syncing pretty well. Tuning to 12.288Mhz I see an indeterminant signal but not a pure carrier. Since it's a clock signal a pure carrier would be unexpected. The signal is not very strong but since everything seems to work I'd guess it's adequate.

FYI - I just completed a JT65 QSO with VE3NDQ, at a distance of 727 miles and 200mW from the Peaberry. So far the BETA firmware is working for me. I do have a couple of questions but not about the firmware so I will start a new thread for those.
73
Dan Malcolm
K4SHQ CFI/II
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Re: BETA firmware PLL fix

Postby k1qn » Tue Mar 10, 2015 2:12 pm

I've had great success with the Peaberry SDR V2, except that I can't work CW. I'm using an old XP machine with PowerSDR. Will this firmware fix the CW problem? Also, how do I upgrade the firmware, and how risky is it?

thanks!

-Al, K1QN
Al Gerheim, K1QN
Celebrating 50 years in ham radio!
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Re: BETA firmware PLL fix

Postby AE9RB » Tue Mar 10, 2015 4:06 pm

Testing the oscillator directly or by sub harmonic sampling is not useful. This does not fix anything other than what I described (which is something only one person reported). This will not fix a software configuration issue.
73 David AE9RB
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Re: BETA firmware PLL fix

Postby W4MMP » Tue Mar 10, 2015 4:08 pm

David,
Please let me know when you have officially released the new firmware so that I may incorporate the changes into my CW firmware.
73
Ron / W4MMP
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Re: BETA firmware PLL fix

Postby AE9RB » Tue Mar 10, 2015 4:33 pm

I pushed all the changes. You might as well merge this right away. Anyone trying your firmware already has the flash tool loaded so they can easily revert to a working version.
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Re: BETA firmware PLL fix

Postby W4MMP » Tue Mar 10, 2015 4:45 pm

Thanks. Will do. I have a new release coming out in a week or two, it frees up the ATU port and uses the AMP port for keying HDSDR.
73
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Re: BETA firmware PLL fix

Postby WB8ENE » Wed Mar 11, 2015 12:04 pm

Ron,

Would it be possible to select which port is used for keying HDSDR? I currently have a Hardrock-50 connected, and don't typically use an ATU. If not, I'll just stick with your current release. It seems to work just fine for me.

73,
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