IQGen

General discussion and support for the Peaberry SDR V1.

IQGen

Postby edingraham » Sat Nov 24, 2012 9:36 pm

why not just draw a couple of FFs ala SoftRock instead of the C and V code?

73, Ed WX4S
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Re: IQGen

Postby AE9RB » Sun Nov 25, 2012 12:29 am

Are you looking at the verilog implementation? The Peaberry will tune down to 120kHz. You can't do that with only two flip flops. It takes at least five. The PLAs for wiring all this up get big and pick up a lot of noise. So I ended up using a hardware counter in the PSoC. I also ground the transmitter I/Q lines when not transmitting which helps keep some noise out of the receiver.
73 David AE9RB
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Re: IQGen

Postby edingraham » Sun Nov 25, 2012 4:34 pm

Verilog implementation? I don't understand what you mean. Didn't you write the code in IQGen.v?

If QSC comes from Si570 (right?) then why divide?

Perhaps a couple of lines of text explaining the purpose and function of IQGen are what I need.
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Re: IQGen

Postby AE9RB » Sun Nov 25, 2012 5:03 pm

Dot V files contain logic written in Verilog. IQGen.v divides the Si570 clock into two clocks that are exactly 90 degrees out of phase.
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Re: IQGen

Postby edingraham » Sun Nov 25, 2012 9:44 pm

Gee, I can ask some silly questions. Thanks for your patience.

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